The present disclosure generally relates to the field of electronics. More particularly, an embodiment of the invention relates to ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells.
As processors increase their processing capabilities, one concern is the amount of additional power consumed by these processors. Increased power consumption may increase heat dissipation issues, decrease battery longevity, and increase the likelihood of thermal damage. To counter these issues, some processors may be operated at lower voltage levels. However, some processor's low voltage performance and yield may be limited by dense memory bit cells. ECC (Error Correction Code) may be utilized to improve yield in some implementation. But, ECC may not be viable for most register files (formed by the memory bit cells) that may be sprinkled across a processor, in part, because the increase in latency due to ECC operations can be prohibitive. Upsizing register file memory bit cells may improve low voltage operations but may also result in lost density and may further fail to solve scaling issues going forward.